Semiconductor devices are becoming smaller and more dense with the evolution of new technology. Therefore, there is a constant demand to increase circuit density and to optimize the real estate available for the circuits. However, increases in circuit density produce a corresponding increase in overall chip failure rates at a time when chip failure rates must decrease to remain competitive. Chip manufacturers are therefore constantly challenged to improve the quality of their products by identifying and eliminating defects and also to enhance their products. Whereas significant improvements are being made to eliminate systematic defects by reducing process variability. Process improvements alone are not sufficient to eliminate all the random defects which effect both yield and reliability. Historically, screening techniques have been employed to improve product failure rates to acceptable levels by culling out many of these random defects.
U.S. Pat. No. 4,291,815 (Gordon, et al.) discloses a ceramic lid assembly which includes an integral heat fusible layer defining a hermetic sealing area provided around the periphery of the ceramic lid for hermetic sealing of semiconductor chips in a flat pack.
U.S. Pat. No. 4,746,583 (Falanga) discloses a ceramic combined cover, where a solder layer in the form of a pre-cut gold-tin solder frame is tack welded onto a gold layer. The gold layer is readily wettable by the solder layer and is also extremely corrosion resistant.
U.S. Pat. No. 5,471,027 (Call, et al.), discloses a method for forming chip carrier with a single protective encapsulant. He specifically teaches the use of a picture-frame type area, which is only on the top surface and away from the edges of the substrate, to seal the cap or cover or heat sink to the substrate using a cap sealant.
However, this invention addresses the issue of optimizing the real estate available on a ceramic substrate by providing a fluid-tight seal to a ceramic chip carrier. This is done by using a novel dual surface seal. Basically, the dual surface seal is at the corner edges of the chip carrier, i.e., a minimal amount of the top-surface real estate of the chip carrier in conjunction with the side-walls of the chip carrier are used to create this dual surface seal. This dual surface seal can be both hermetic and non-hermetic.